1. Field of the Invention
The subject matter of the present application relates to microelectronic devices, particularly microelectronic devices having semiconductor devices incorporated therein, and their fabrication. More specifically, the present subject matter relates to microelectronic devices which include an air gap between metal lines therein, and the fabrication thereof.
2. Description of the Related Art
FIG. 1 is a sectional view illustrating a stage in a method of fabricating a microelectronic element 10 such as a semiconductor wafer or semiconductor chip according to the prior art. The prior art fabrication method has application in “Back End Of Line” (BEOL) fabrication of a series of dielectric layer 110 and metal wiring lines 120 therein which support operation of semiconductor devices 102 provided within a semiconductor region 100 of the microelectronic element. Structure (shown generally at 105), which may include dielectric material, semiconductive or conductive features, e.g., vias, lines, etc., typically connects the metal wiring lines 120 with the semiconductor devices 102, although not specifically shown in FIG. 1.
Typically, the metal lines 120 are provided as damascene structures, i.e., inlaid at a surface 115 of the dielectric layer 110, and one or more layers 112 of various conductive or non-conductive materials can line walls of the dielectric layer 110 to promote adhesion thereto, as a barrier to inhibit diffusion of materials, as a seed layer for electroplating a fill metal or for other purposes. A dielectric cap layer 114 may overlie the dielectric layer 110 and the metal wiring lines 120.
As further shown in FIG. 1, a mask layer 116 can overlie the dielectric cap for use in subsequent fabrication steps. The mask layer has a multiplicity of holes aligned with the dielectric layer 110 and with the metal lines 120. The holes in the mask layer 116 can be randomly distributed over the cap layer 114. As a result, the mask holes overlie the metal lines 120 and areas 124 of the dielectric layer between the metal lines 120. A second mask layer 125 which lacks holes can overlie one or more of the metal lines 120′ and other areas 126 of the dielectric layer to protect such metal line 120′ and areas 126 from subsequent processing.
As illustrated in FIG. 2, a directional etch process, such as a reactive ion etch (“RIE”) process, removes portions of the cap dielectric layer 114 and dielectric layer 110 which are aligned with the holes in the mask layer 116 to form recesses 130. Due to the nature of RIE which includes bombardment of ions, surfaces which are exposed during RIE can be eroded. Thus, surfaces of the metal lines 120 which are aligned with the holes in the masking layer can become eroded, leaving recesses 122 therein.
FIG. 3 illustrates a subsequent stage of fabrication in which a post-RIE cleaning process and a further etch process are employed. For example, an isotropic wet etch process can be employed to remove material exposed at the walls and bottoms of the recesses 130 (FIG. 2) in the dielectric layer 110 to form larger recesses 132. Such recesses 132, when they remain occupied by air or other gas after subsequent processing, provide voids between metal lines 120 of the structure.
FIG. 3 further illustrates an effect of the RIE and subsequent etch processes on the metal lines. Exposure of the metal lines 120 to the directional and subsequent isotropic etch processes leaves recesses 122′ in the metal lines which typically have uneven and often rough surfaces 128.